Quick Detail:
XC9500 In-System Programmable CPLD Family
Description:
The XC9500 CPLD family provides advanced in-system programming and
test capabilities for high performance, general purpose logic
integration. All devices are in-system programmable for a minimum
of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG)
boundary-scan support is also included on all family members.
As shown in Table 1, logic density of the XC9500 devices ranges
from 800 to over 6,400 usable gates with 36 to 288 registers,
respectively. Multiple package options and associated I/O capacity
are shown in Table 2. The XC9500 family is fully pin-compatible
allowing easy design migration across multiple density options in a
given package footprint.
The XC9500 architectural features address the requirements of
in-system programmability. Enhanced pin-locking capability avoids
costly board rework. An expanded JTAG instruction set allows
version control of programming patterns and in-system debugging.
In-system programming throughout the full device operating range
and a minimum of 10,000 program/erase cycles provide worry-free
reconfigurations and system field upgrades.
Advanced system features include output slew rate control and
user-programmable ground pins to help reduce system noise. I/Os may
be configured for 3.3V or 5V operation. All outputs provide 24 mA
drive.
Applications:
• High-performance
- 5 ns pin-to-pin logic delays on all pins
- fCNT to 125 MHz
• Large density range
- 36 to 288 macrocells with 800 to 6,400 usable gates
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within
Function Block
- Global and product term clocks, output enables, set and reset
signals
- Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
- Programmable power reduction mode in each macrocell
- Slew rate control on individual outputs
- User programmable ground pin capability
- Extended pattern security features for design protection
- High-drive 24 mA outputs
- 3.3V or 5V I/O capability
Specifications:
Datasheets | XC95288 Series
XC9500 CPLD Family |
PCN Obsolescence | XC1700, 5200, HQ, SCD Families 19/Jul/2010 |
Standard Package | 24 |
Category | Integrated Circuits (ICs) |
Family | Embedded - CPLDs (Complex Programmable Logic Devices) |
Series | XC9500 |
Packaging | Tray |
Programmable Type | In System Programmable (min 10K program/erase cycles) |
Delay Time tpd(1) Max | 20.0ns |
Voltage Supply - Internal | 4.5 V ~ 5.5 V |
Number of Logic Elements/Blocks | 16 |
Number of Macrocells | 288 |
Number of Gates | 6400 |
Number of I /O | 168 |
Operating Temperature | -40°C ~ 85°C |
Mounting Type | Surface Mount |
Package / Case | 208-BFQFP Exposed Pad |
Supplier Device Package | 208-PQFP (28x28) |
Competitive Advantage:
Warranty :180 days !
Free shipping: Order over $1000 win a free shipment fee
(goods weight below 3Kg) ,during 20130901-20130930 .
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